The present invention relates in general to integrated circuits and in particular to differential input circuits.
To meet the demands of today's applications, integrated circuits are being designed to operate at higher speeds with lower power supply voltages. One technique for enabling high frequency operation at lower voltages is differential signaling. In differential signaling, logic levels are represented by the difference between a pair of complementary signals. Instead of processing signals that swing between the power supplies, circuits designed to process differential signals need only detect a relatively small difference in voltage between the two complementary signals. The much smaller voltage swing and the lower voltage level characteristics of differential signaling facilitate high speed operation at lower voltages.
Integrated circuits that receive differential signals require a differential input buffer that properly detects the logic level of the received signal. The design of a differential input buffer is generally dictated by a set of specifications that defines the speed and input voltage level range. For example, to receive LVDS signals, a differential input buffer is required to properly detect the logic levels of the differential input signal over a relatively wide common mode range. The common mode voltage of the LVDS input signal (Vin,cm) may range from 0 volts to 2.4 volts. This places stringent requirements on the operation of the input buffer. For example, an input buffer that includes a differential input pair of n-channel transistors can properly detect a differential input signal as long as Vin,cm remains high enough to overcome the threshold voltage of the n-channel transistors. When Vin,cm approaches 0 volts neither of the n-channel input transistors in the differential pair can turn on, resulting in the failure of the circuit to properly detect the LVDS logic levels. Constructing the differential input pair with p-channel transistor will similarly fail at the higher Vin,cm levels.
A number of innovative circuit techniques addressing the above and other constraints when designing differential input buffers, are described in commonly-owned U.S. Pat. No. 6,236,231, to Nguyen et al., which is hereby incorporated by reference in its entirety. There, the inventors connected two differential input pairs in parallel receiving the differential input signal; one pair with n-channel input transistors (n-diff pair) and the other pair with p-channel input transistors (p-diff pair). With this design, the n-diff pair operates at the higher end of the input common mode voltage Vin,cm, and as the Vin,cm moves toward 0 volts the n-diff pair turns off but the p-diff pair turns on to detect the input signal. This expands the operational range of the input circuit.
The parallel n-diff pair and p-diff pair input buffer works well as long as the power supply voltage VCC remains above the sum of the n-channel transistor threshold voltage Vtn and the absolute magnitude of the p-channel transistor threshold voltage |Vtp|, (i.e., VCC>[Vtn+|Vtp|]). For example, given an n-channel threshold voltage Vtn of 0.7 volts and a p-channel threshold voltage Vtp of −0.7 volts, the power supply voltage for the differential input buffer must be greater than 1.4 volts in order for the circuit to be functional. If the power supply voltage drops below 1.4 volts, there will be a voltage range within which neither the n-channel transistors nor the p-channel transistors has high enough gate-to-source (Vgs) voltage to turn on. In the above example, with a power supply voltage VCC of 1.2 volts, an input differential signal with a common mode voltage around 0.6 volts will not be sufficient to turn on either the p-channel transistor or the n-channel transistor.
To overcome the above problem that is encountered at lower power supply voltages, either a separate and higher power supply for the I/O circuitry can be provided, or the Vin,cm can be shifted away from the failure region. Both these solutions, however, have limitations and drawbacks. The separate I/O power supply can introduce additional I/O noise and if provided externally requires additional power pad and bus routing. Shifting the common mode voltage away from the failure region requires extra control circuitry that adds to circuit complexity and limits the frequency of operation of the circuit.
There is therefore a need for further improvements in design of differential output buffers that efficiently enable the circuit to operate with low power supply voltages.